1. Field of the Invention
The present invention relates, in general, to methods for forming contacts in a semiconductor device through which devices are connected with each other and, more particularly, to methods for forming contacts in semiconductor device, capable of securing allowance enough to prevent from forming a short circuit between the conductive films.
2. Description of the Prior Art
Increases in the degree of integration of semiconductor devices is usually accompanied by reducing the area for the unit cell, forcing the contacts formed on a semiconductor substrate to be diminished in size. This shortens the distance between electrical conductors formed in a semiconductor device. For increases in the degree of integration, it is therefore excessively required to develop a technology which is capable of forming contacts as well as securing insulation among the electrical conductors.
Especially, in forming contacts of bit line and/or charge storage electrode between gate electrodes or between word lines in a highly integrated DRAM cell, there is increasing demand for a technology preventive of short circuits formed between the bit line or charge storage electrode and the gate electrode or word line, with enough allowance.
In order to better understand the background of the present invention, a description will be made in conjunction with a conventional formation method for contact and accompanying problems by referring FIGS. 1A through 1C.
First, on a silicon substrate 1, there are formed gate insulating films 20, gate electrodes 2, first insulating films 3 and spacer insulating films 4, as shown in FIG. 1A. Thereafter, the resulting structure of FIG. 1A is subjected to planarization by coating thereon a planarization film 13, an insulating film, which is then opened with a mask at a predetermined area to form a contact hole between the electrodes 2, followed by deposition of a conductive film 14 over the contact hole to form a contact, as shown in FIG. 1B.
However, this conventional method is highly apt to cause problems. For example, the distance between the gate electrodes 2 becomes shortened in a highly integrated semiconductor device, giving small allowance to the mask process. In other words, as a result of carrying out the mask process to form the contact hole after the coating of the planarization film 13, the contact experiences short circuit with the gate electrode, as shown in FIG. 1C (by circle 21).